A Self-Timed Multiplier using Conditional Evaluation
نویسندگان
چکیده
A low-power, self-timed, CMOS array multiplier, optimized for asynchronous DSP but also applicable to synchronous DSP applications is presented. In order to reduce average power consumption, a strategy termed conditional-evaluation is introduced whereby addition is carried out only in rows of the carry-save array whose bit-product is non-zero. Simulation results are presented for a transistor-level, 8-bit x 8-bit implementation which shows an average-case energy consumption of 73pJ with an average delay of 30.5ns.
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